Program

2024/9/10

Track 1 Track 2 Exhibition

9:00 am

9:30 am

9:40 am

10:10 am

10:40 am

11:10 am

11:30 am

12:30 pm

1:30 pm

1:50 pm

2:10 pm

2:30 pm

2:50 pm

3:10 pm

3:30 pm

3:50 pm

4:10 pm

4:30 pm

4:40 pm

Welcome

9:00 am – 9:30 am (30 min)
Track 1, Track 2

Exhibition Day 1

9:00 am – 5:00 pm (480 min)
Exhibition

Opening

9:30 am – 9:40 am (10 min)
Track 1, Track 2
Steering Committee

Keynote 1

9:40 am – 10:10 am (30 min)
Track 1, Track 2
Alessandra Nardi PhD – Synopsys Executive Director & Chair of Accellera Functional Safety Working Group

Keynote 2

10:10 am – 10:40 am (30 min)
Track 1, Track 2
Erik Seligman, Sr Product Engineering Architect, Cadence

Keynote 3

10:40 am – 11:10 am (30 min)
Track 1, Track 2
Chilai Huang, Senior Director, R&D, Siemens EDA

Morning Break

11:10 am – 11:30 am (20 min)
Track 1, Track 2

Panel Discussion

11:30 am – 12:30 pm (60 min)
Track 1, Track 2
Moderator: Prof Chung-Yang (Ric) Huang, National Taiwan University

Lunch Break

12:30 pm – 1:30 pm (60 min)
Track 1, Track 2

Session 1.1

1:30 pm – 1:50 pm (20 min)
Track 1
Truechip

Session 2.1

1:30 pm – 1:50 pm (20 min)
Track 2
TESDA

Session 1.2

1:50 pm – 2:10 pm (20 min)
Track 1
AMD

Session 2.2

1:50 pm – 2:10 pm (20 min)
Track 2
NTHU

Session 1.3

2:10 pm – 2:30 pm (20 min)
Track 1
Cadence

Session 2.3

2:10 pm – 2:30 pm (20 min)
Track 2
Synopsys

Session 1.4

2:30 pm – 2:50 pm (20 min)
Track 1
MediaTek

Session 2.4

2:30 pm – 2:50 pm (20 min)
Track 2
Synopsys

Afternoon Break 1

2:50 pm – 3:10 pm (20 min)
Track 1, Track 2

Session 1.5

3:10 pm – 3:30 pm (20 min)
Track 1
Silicon Interfaces

Session 2.5

3:10 pm – 3:30 pm (20 min)
Track 2
MediaTek and Cadence

Session 1.6

3:30 pm – 3:50 pm (20 min)
Track 1
Andes

Session 2.6

3:30 pm – 3:50 pm (20 min)
Track 2
Cadence

Session 1.7

3:50 pm – 4:10 pm (20 min)
Track 1
Synopsys

Session 2.7

3:50 pm – 4:10 pm (20 min)
Track 2
Siemens

Session 1.8

4:10 pm – 4:30 pm (20 min)
Track 1
Andes

Session 2.8

4:10 pm – 4:30 pm (20 min)
Track 2
Siemens

Afternoon Break 2

4:30 pm – 4:40 pm (10 min)
Track 1, Track 2

Awards

4:40 pm – 5:00 pm (20 min)
Track 1, Track 2

2024/9/11

Track 1 Track 2 Exhibition

9:00 am

9:30 am

9:40 am

10:00 am

10:20 am

10:40 am

11:00 am

11:10 am

11:20 am

11:30 am

12:10 pm

1:30 pm

3:30 pm

Exhibition Day 2

9:00 am – 3:30 pm (390 min)
Exhibition

RISC-V Taipei Day

9:30 am – 11:10 am (100 min)
Track 1

Session 3.1

9:40 am – 10:00 am (20 min)
Track 2
Robert Chen, CEO of TESDA

Session 3.2

10:00 am – 10:20 am (20 min)
Track 2
Nitin Kishore, CEO of Truechip

Session 3.3

10:20 am – 10:40 am (20 min)
Track 2
Seungwhun Paik, CEO of Baum Design Systems

Session 3.4

10:40 am – 11:00 am (20 min)
Track 2
Vega Lin, Senior Application Engineer, Perforce Software

Session 3.5

11:00 am – 11:20 am (20 min)
Track 2
YiChiang Chang, Senior Field Application Engineer, Arteris

Morning Break

11:10 am – 11:30 am (20 min)
Track 1

Closing – DVCon Taiwan 2024 Feedbacks

11:20 am – 12:10 pm (50 min)
Track 2

RISC-V Taipei Day

11:30 am – 12:10 pm (40 min)
Track 1

Lunch Break

12:10 pm – 1:30 pm (80 min)
Track 1, Track 2

RISC-V Taipei Day

1:30 pm – 4:30 pm (180 min)
Track 1, Track 2