Track 1 Track 2 Exhibition
8:30 am
9:00 am
9:20 am
9:50 am
10:20 am
10:40 am
11:10 am
11:40 am
12:30 pm
1:30 pm
2:00 pm
2:30 pm
3:00 pm
3:30 pm
4:00 pm
4:30 pm
5:00 pm
5:30 pm
6:00 pm
Keynote 1: Accellera, Standards, and Semiconductor Supply Chain
9:20 am – 9:50 am (30 min)
Track 1, Track 2
Lu Dai – Chair of Accellera and Senior Director at Qualcomm
Keynote 2 – Next Generation EDA – Leveraging AI to Achieve the Next 10x
9:50 am – 10:20 am (30 min)
Track 1, Track 2
Dr. Paul Cunningham – Senior Vice President and General Manager, Cadence
Keynote 3: Autonomous Verification: Are we there yet?
10:40 am – 11:10 am (30 min)
Track 1, Track 2
Ajay Singh – Senior Vice President, Synopsys
Keynote 4 – Smart Verification: Faster is not enough!
11:10 am – 11:40 am (30 min)
Track 1, Track 2
Abhi Kolpekwar – VP & General Manager of Digital Verification Technologies, Siemens EDA
Panel: How to Develop Future Talents in Design Verification
11:40 am – 12:30 pm (50 min)
Track 1, Track 2
Paper 1.1 – Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator
1:30 pm – 2:00 pm (30 min)
Track 1
Chi-Ming Li – Synopsys
Paper 2.1 – Tutorial – AI-Driven Verification
1:30 pm – 2:00 pm (30 min)
Track 2
Tsung-Hsien (Curtis) Tsai – Cadence
Paper 1.2 – UVM-based extended Low Power Library package with Low Power Multi-Core Architectures
2:00 pm – 2:30 pm (30 min)
Track 1
Priyanka Gharat – Silicon Interfaces
Paper 2.2 – Tutorial – Debug Automation with AI
2:00 pm – 2:30 pm (30 min)
Track 2
Craig Yang – Synopsys
Paper 1.3 – Scoreboards and Checkers Memory, TLB and Cache
2:30 pm – 3:00 pm (30 min)
Track 1
Chih-Hsiang Liu – Siemens EDA
Paper 2.3 – Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset
2:30 pm – 3:00 pm (30 min)
Track 2
Gopi Srinivas Deepala – Silicon Interfaces
Paper 1.4 – Improve the quality of SystemC IPs through coverage-driven random verification
3:00 pm – 3:30 pm (30 min)
Track 1
Trung Pham – Renesas
Paper 2.4 – Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY
3:00 pm – 3:30 pm (30 min)
Track 2
Harshdeep Verma – Cadence
Paper 1.5 – SAR ADC Layout Generation Using Digital Place-and-Route Tools
4:00 pm – 4:30 pm (30 min)
Track 1
Yao-Hung Tsai – NTU
Paper 2.5 – Formal Sign-off methodology for IP blocks
4:00 pm – 4:30 pm (30 min)
Track 2
Anna Chang – Google
Paper 1.6 – Design and Verification of a Cell-Based PLL using an Optimized DCO
4:30 pm – 5:00 pm (30 min)
Track 1
Yi-Sheng Wang – NTHU
Paper 2.6 – A Novel Approach to Accelerate Latency of Assertion Simulations
4:30 pm – 5:00 pm (30 min)
Track 2
Dr. Jack Yen – Synopsys
Paper 1.7 – Building a Virtual Driver for Emulator
5:00 pm – 5:30 pm (30 min)
Track 1
Chih Chiang Chen – Andes
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