Title: Not Your Father’s Formal Verification

Formal Verification has rapidly grown over the past two decades. From a niche area dominated by specialists to provide “last mile” verification, it has become a mainstream tool essential to any serious validation flow.   Yet because of the way it evolved, many current users are not yet leveraging some of the powerful new techniques developed over the last decade.   A validation engineer who wants to maximize design and validation efficiency should make sure not to miss these new developments. In this talk we will review how serious production-level Formal took off in the ancient days of the 2010s, which cool new formal technologies every engineer should be using today, and our vision of the amazing ways Formal Verification will continue to evolve.

Speaker: Erik Seligman, Sr Product Engineering Architect, Cadence

Erik Seligman is a Senior Product Engineering Architect at Cadence, and lead author of the popular text “Formal Verification:  An Essential Toolkit for Modern VLSI Design”.   Before joining Cadence, he retired from Intel after 27 years, during which he worked on Formal Verification for many generations of Intel processors and chipsets.