Title: AI for Formal Engineering and Formal Engineering for AI – What catches up fast?
- AI-powered formal/verification tools
- Challenges and opportunities for AI-assisted formal engineering
- Experiences in applying formal engineering on AI chip designs
- Challenges and opportunities in formal engineering for AI chip designs
Moderator:
Chung-Yang (Ric) Huang, Professor of Dept. of Electrical Engineering and Graduate Institute of Electronic Engineering, National Taiwan University
Prof. Huang received his BS and PhD degrees from National Taiwan University (NTU) and University of California, Santa Barbara (UCSB), respectively. Before joining NTU as a faculty member in 2004, he was one of the earliest employees (3rd) of the successful formal verification startup company, Verplex Systems, which created Conformal, a tool that has around 60% worldwide market now, before being acquired by Cadence.
Prof. Huang is a prominent scholar in both research and teaching. He broke the record in NTU by receiving the Outstanding Teaching Awards twice in the first 8 years of service, which is the shortest possible time for a new faculty member. Soon after, he was bestowed tenure-ship in 2011. He is also a renowned researcher in formal verification, a consultant in Cadence, the chair of IEEE CEDA Taipei Chapter. His achievements stretches beyond personal accomplishments, as he also lead students to win the most number of ACM CADathlon contest awards.
Prof. Huang is also very experienced in entrepreneurship. He helped NTU to establish the Creativity and Entrepreneurship Program, NTU Garage, Entrepreneurs Association, NTU Angel Club, and Entrepreneur Center, etc. In 2015, he decided to put aside these responsibilities to startup Yoctol Info Inc.
Panelist: Sandeep Jana, Sr. Director, R&D, Synopsys India Pvt. Ltd.
Sandeep has 20+ years of experience in EDA industry , specialization in RTL synthesis and Formal verification. Leading VC Formal R&D team in Synopsys India. R&D Architect and owner of several apps of VC Formal. Have 2 patents and multiple publications.
Panelist: Chilai Huang, Avery BU Lead of Siemens EDA
Mr. Huang got his Ph.D. in 1982, and he has been working on the EDA business since then. He was the co-founder with Dr. Prabhu Goel of Gateway Design Automation, Inc., where he and Mr. Phil Moorby worked on the language definition and first implementation of Verilog. Since then, he has worked on fault simulation, timing verification, and synthesis technologies. Specifically, he was responsible for Cadence’s RTL synthesis effort for several years — eventually leading the whole synthesis project. In 1998 he left Cadence to start Avery. Besides working on enhancing Verilog’s verification capabilities, parallel simulation, and mixed logic/symbolic simulation, Avery has been working in the Verification IP domain; first on PCIe 1.1, then USB 2.0, Sata, AMBA, etc. Avery has established itself to be the leader in the verification IP area, especially PCIe/NVMe/CXL. Avery merged into Siemens EDA (originally Mentor Graphics) in March 2023.
Panelist: Chris Komar, Sr Product Engineering Group Director
Chris brings over two decades of experience in formal verification. Starting his career as a designer, Chris transitioned to the formal verification domain in the early 2000s by joining Verplex, where he honed his expertise in formal equivalency checking and was exposed to early formal property verification tools. Shortly after Cadence’s acquisition of Verplex in 2003, Chris dedicated his focus to formal property verification and its applications. He has been instrumental in developing and influencing widely-used formal applications. Currently, Chris serves as the Senior Product Engineering Group Director for Jasper at Cadence Design Systems, leading the Product Engineering team responsible for the entire Jasper platform. A holder of multiple patents related to formal verification and its applications, Chris remains passionate about expanding the impact and reach of formal verification technologies.