Title: Left-shifting Testbench Development Using Environment Inversion in UVM

Speaker: Yu-Ju Su, Synopsys

Abstract—Minimizing time-to-market is crucial for hardware verification engineers. The Universal Verification Methodology (UVM) offers testbench modularity and reusability which significantly improves testbench development efficiency. However, UVM’s effectiveness is still restricted by design readiness. Conventional approaches require a design before testbench bring-up and thus creates a bottleneck. This paper proposes the Environment Inversion Methodology, a novel approach that leverages UVM’s framework while overcoming the dependency on design. We introduce the Design Under Test Double (DUTD), a virtual representation of the design seamlessly integrated within the UVM environment. This enables comprehensive verification activities even before the actual design is in place.