Program Grid – 2026

2026/09/08

 
Show tracks
Time Track 1 Track 2 Track 3
09:00 – 09:10
Opening — Lu Dai, Chairman of the Board, Accellera Systems Initiative
09:10 – 09:20
Opening — Robert, Chi-Kang Chen, General Chair, DVCon Taiwan
09:20 – 10:00
Keynote Speaker 1 — Richard An, Realtek
ModeratorYung-Jen Chen, Realtek
Keynote SpeakerRichard An, Realtek
DetailsTopic: Beyond Verification Automation
How AI Will Redefine Semiconductor Design Verification
Abstract: TBD
10:00 – 10:40
Keynote Speaker 2 — Moses Satyasekaran, Siemens EDA
ModeratorMichael Chiang, Siemens EDA
Keynote SpeakerMoses Satyasekaran, Siemens EDA
DetailsTopic: Agentic AI and the Rise of Design & Verification Scientist
Abstract: The complexity of modern SoC design has outpaced our methodologies, and the wall between design and verification has made it worse. Agentic AI solves both. Autonomous systems that reason, plan, and adapt across the chip development lifecycle don’t just accelerate workflows; they dissolve boundaries between creation and validation entirely. Semantic layers unite isolated EDA tools into collaborative, context-aware partners, giving rise to the Design & Verification Scientist: an engineer orchestrating intelligence across the full flow to achieve trusted RTL signoff at unprecedented speed and confidence. The silo era is ending. The scientist era is beginning.
Speaker BioMoses Satyasekaran is Director of Product Management for Design Verification Technology at Siemens EDA, where he leads strategy for simulation and functional verification. He began his career at Xilinx in applications engineering and product marketing before moving into EDA product leadership at Siemens. Moses frequently speaks at industry events, including Siemens Verification Academy Live and User2User, on topics like simulation productivity, debug, and AI-driven verification workflows. He is based in the Pacific Northwest and is passionate about helping engineering teams close the gap between raw simulation speed and true verification productivity.
10:40 – 11:00
Morning Break (Setting up the stage for Panel Discussion)
11:00 – 12:00
Panel Discussion
ModeratorProf. Kai-Chiang Wu, 吳凱強教授
Director, Institute of Computer Science and Engineering, National Yang Ming Chiao Tung University
Panelists1. Richard An, 安效真, Realtek
2. Grant Pan, Synopsys
3. Moshik Rubin, Cadence
4. Moses Satyasekaran, Siemens EDA
5. William Wang, Founder and CEO, ChipAgents
TopicHave we now relieved from design and verification complexities through current Agentic AI flow?
12:00 – 13:20
Lunch Break
Track Focus Track 1-1IP Verification & Debug Track 2-1Agentic AI – I Track 3-1Modeling & Coverage – I
13:20 – 13:40
Session 1.1DVCon Japan
SpeakerWakabayashi-san
TopicDVCon Japan
Sessions 2.127. “Agentic Coverage Closure: Accelerating Functional Verification via Trusted Multi-Agent Platforms”
SpeakerDanny Rose
ChipAgents
Topic27. “Agentic Coverage Closure: Accelerating Functional Verification via Trusted Multi-Agent Platforms”
Sessions 3.1Cadence Tutorial 2
SpeakerFiona Lai
TopicCadence Tutorial 2
13:40 – 14:00
Session 1.2TBD
SpeakerCadence
TopicTBD
Sessions 2.216. “AI-Driven Handoff Acceleration: Slashing BIU Verification Loops via Autonomous UVM Generation”
SpeakerYong-Nan Yang
Andes
Topic16. “AI-Driven Handoff Acceleration: Slashing BIU Verification Loops via Autonomous UVM Generation”
Sessions 3.207. “Breaking the PAM4 Barrier: A Coverage Driven Framework for PCIe Gen6/Gen7 Equalization and Redo Equalization”
SpeakerSatish Kumar Padhi
Cadence
Topic07. “Breaking the PAM4 Barrier: A Coverage Driven Framework for PCIe Gen6/Gen7 Equalization and Redo Equalization”
14:00 – 14:20
Session 1.3
Sessions 2.318. “Accelerating Complex Memory LSU and Ordering RTL Customization via Autonomous AI Agents”
SpeakerYi Chieh Chen
Andes
Topic18. “Accelerating Complex Memory LSU and Ordering RTL Customization via Autonomous AI Agents”
Sessions 3.311. “Practical Strategies for Accelerated SoC Sign-off”
SpeakerVinod Kumar Balure
Cadence
Topic11. “Practical Strategies for Accelerated SoC Sign-off”
14:20 – 14:40
Session 1.48. “Enabling Cross-Transport NVMe Verification Reuse Using a Modular Layering Architecture”
SpeakerRajan Jani
Cadence
Topic8. “Enabling Cross-Transport NVMe Verification Reuse Using a Modular Layering Architecture”
Sessions 2.420. “Black-Box FPGA Prototyping and Fault Injection Verification of a Dual-CPU SoC via Autonomous, High-Efficiency RCA Pipelines with AI Agent”
SpeakerEric Lee
Whalechip
Topic20. “Black-Box FPGA Prototyping and Fault Injection Verification of a Dual-CPU SoC via Autonomous, High-Efficiency RCA Pipelines with AI Agent”
Sessions 3.415. “AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage”
SpeakerDharini Subashchandran
Cadence
Topic15. “AI-Augmented Constrained Randomized Framework with Feature-Specific Dynamic Customization for Lpddr6 based design Verification Coverage”
14:40 – 15:00
Session 1.528. “How Agents Make Formal Verification Scalable for Modern Designs”
SpeakerDanny Rose
ChipAgents
Topic28. “How Agents Make Formal Verification Scalable for Modern Designs”
Sessions 2.524. “IP Functional Model Verification with HW-Focused AI Agents”
SpeakerYen-Jung Lee
eMemory
Topic24. “IP Functional Model Verification with HW-Focused AI Agents”
Sessions 3.526. “Accelerating Functional Safety Fault Debug Using AI-Powered WaveMining and Signal Analysis”
SpeakerMadhuri Yellisetti
Cadence
Topic26. “Accelerating Functional Safety Fault Debug Using AI-Powered WaveMining and Signal Analysis”
15:00 – 15:20
Afternoon Break
Track Focus Track 1-2CDC & Academia Track 2-2Agentic AI – II Track 3-2Modeling & Coverage – II
15:20 – 15:40
Session 1.6 ( 40 mins talk )04. “CDC-RDC Verification Standard 1.0 for Interoperable Abstract Model”
SpeakerLee Fueng Yap
Dammy Olopade
Suman Chalana
Accellera CDC-RDC WG
Topic04. “CDC-RDC Verification Standard 1.0 for Interoperable Abstract Model”
Sessions 2.617. “No Anymore Tedious but Necessary, No Anymore Wild Guess”
SpeakerTsungyu Tsai
Siemens EDA
Topic17. “No Anymore Tedious but Necessary, No Anymore Wild Guess”
Sessions 3.630. “Closing the Verification Blind Spot in AI-Accelerated SoC Design”
SpeakerYale Lee
Nurol
Topic30. “Closing the Verification Blind Spot in AI-Accelerated SoC Design”
15:40 – 16:00
Sessions 2.713. “Toward AI-Native Power Optimization”
SpeakerSeungwhun Paik
Baum
Topic13. “Toward AI-Native Power Optimization”
Sessions 3.721. “Using AI to Help Light Up Latency Debug with Transactions”
SpeakerRich Edelman
Simems EDA
Topic21. “Using AI to Help Light Up Latency Debug with Transactions”
16:00 – 16:20
Session 1.814. “Beyond Boolean Limits Next-Generation Static Verification for Microarchitectural Integrity, CDC, Connectivity, and Hardware Security”
SpeakerVikas Sachdeva
Real Intent
Topic14. “Beyond Boolean Limits Next-Generation Static Verification for Microarchitectural Integrity, CDC, Connectivity, and Hardware Security”
Sessions 2.832. “From Spec to Sign-Off: Automating the SoC Design Verification Lifecycle with Agentic AI”
SpeakerYaswani Priyanka Vempali
Marvell
Topic32. “From Spec to Sign-Off: Automating the SoC Design Verification Lifecycle with Agentic AI”
Sessions 3.806. “From RTL+Design Spec to Cycle-True C: An AI-Assisted Bit-Match Verification Flow for TX DAC CAL”
SpeakerTiger Chen
Marvell
Topic06. “From RTL+Design Spec to Cycle-True C: An AI-Assisted Bit-Match Verification Flow for TX DAC CAL”
16:20 – 16:40
Session 1.905. “Feature-Centric Code Coverage (FCC): Transforming RTL Code Coverage into Dynamic Feature Verification Artifacts”
SpeakerThinh Ngo
Nam Can Tho University
Topic05. “Feature-Centric Code Coverage (FCC): Transforming RTL Code Coverage into Dynamic Feature Verification Artifacts”
Sessions 2.919. “Integrating a Domain-Specific AI Agent Framework and Open GAI Standards for Accelerating Shift-Left RTL Design and Verification”
SpeakerChenlin Huang
MediaTek
Topic19. “Integrating a Domain-Specific AI Agent Framework and Open GAI Standards for Accelerating Shift-Left RTL Design and Verification”
Sessions 3.929. “From Assumption to Confidence: Closing the Spec-to-Silicon Gap using HW/SW Co-verification”
SpeakerShih-Chang Hung
Siemens EDA
Topic29. “From Assumption to Confidence: Closing the Spec-to-Silicon Gap using HW/SW Co-verification”
16:40 – 17:00 —
Sessions 2.A31. “AIDE: Extending AI-Augmented Development Environments to CAD, Verification, and End-User Applications”
SpeakerVahagn Poghosyan
Instigate Design
Topic31. “AIDE: Extending AI-Augmented Development Environments to CAD, Verification, and End-User Applications”
Sessions 3.A
17:00 – 17:30
Closing, Awards, and Lucky Draw.

Showing Track 1, Track 2, and Track 3.