Speaker: Dr. Paul Cunningham

Dr. Paul Cunningham has served as Senior Vice President and General Manager of the System Verification Group (SVG) in Cadence since March 2021, running the division since 2018. His responsibilities include logic simulation, emulation, prototyping, formal verification, Verification IP, and functional debug. Prior to this role, Cunningham was responsible for Cadence’s frontend digital design tools including logic synthesis and design-for-test.

Dr. Cunningham joined Cadence in 2011 via the acquisition of Azuro, a startup developing concurrent physical optimization and useful skew clock tree synthesis technologies, where he was a co-founder and CEO. Dr. Cunningham holds a MS and a PhD in Computer Science from the University of Cambridge in the UK.

Abstract: IC device complexity continues to increase, driven by expanding demand for SoCs across industries like hyperscale compute, automotive, IoT, aerospace, and mobile.  Increased complexity and demand for devices has resulted in more design starts, with not enough engineering resources to meet the demand.  As Artificial Intelligence and Machine Learning become more and more accessible across the technology landscape, EDA has the opportunity to leverage these technologies to increase overall productivity through both automation, and catalyzation of the human in the loop.  Cadence SVP and GM Paul Cunningham will discuss this current IC landscape, and how AI can help EDA drive the next 10x increase in engineering productivity.

Language: English