Title: Empowering Innovation in Logic Verification: Harnessing Collective Wisdom Across Tools, Processes, and People

Speaker: Chilai Huang, Senior Director, R&D, Siemens EDA

Mr. Huang got his Ph.D. in 1982, and he has been working on the EDA business since then. He was the co-founder with Dr. Prabhu Goel of Gateway Design Automation, Inc., where he and Mr. Phil Moorby worked on the language definition and first implementation of Verilog. Since then, he has worked on fault simulation, timing verification, and synthesis technologies. Specifically, he was responsible for Cadence’s RTL synthesis effort for several years — eventually leading the whole synthesis project. In 1998 he left Cadence to start Avery. Besides working on enhancing Verilog’s verification capabilities, parallel simulation, and mixed logic/symbolic simulation, Avery has been working in the Verification IP domain; first on PCIe 1.1, then USB 2.0, Sata, AMBA, etc. Avery has established itself to be the leader in the verification IP area, especially PCIe/NVMe/CXL. Avery merged into Siemens EDA (originall y Mentor Graphics) in March 2023.