Speaker: Ajay Singh

Ajay Singh is senior vice president and leader of the Design Creation and Verification (DCV) Group at Synopsys. Ajay leads the Synopsys R&D team responsible for developing EDA tools for design synthesis (Design Compiler, Fusion Compiler), design exploration (RTL Architect), logic equivalence (Formality), dynamic simulation (VCS), static verification (VC SpyGlass), formal verification (VC Formal), debug (Verdi), and fault simulation (VC Z01X).

Ajay holds a bachelor’s degree in Electronics and Telecommunication from College of Engineering, Pune, India. He has 30+ years of EDA industry experience.

Abstract:

We are now in the world of Smart Everything from voice assistants, advanced robotics, drone-based delivery to autonomous cars and chatbots. This begs the question, how are we doing in design verification? Design verification is one of the most expensive and time-consuming activities for any chip design. Moreover, every year the cost of design verification grows exponentially and despite that ½ of design re-spins are caused by functional or logic bugs. When we consider where time is spent in verification, coverage convergence and debug consume 70% of overall verification time. In addition to time spent, misinterpretation of specifications is a major source of bugs. With the rapid evolution of AI/ML technologies, how can we automate some or many of these activities? What technologies are available today and what is on the horizon? With the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification? Just like there are 6 levels of driving automation, from driver assistance to conditional automation to full automation, what level is the current state of verification? This keynote address will explore these topics and look ahead to the future of autonomous verification.

Language: English