Session: UVM

Session Chair: SJ Wu, Andes

Title: Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator

Language: Mandarin

Abstract—Verification engineers put in a great effort designing stimulus for bug hunting and coverage closure. In Constrained random verification (CRV) methodology like UVM, generating versatile stimulus for stressing DUT usually requires a lot of hand-crafted sequence classes with constraints for addressing specific verification concerns. As the project goes on, the number of such sequence classes surge which eventually leads to combinatorial explosion. In this paper we propose a scalable way to design and manage sequence classes using the sequence decorator, which is a structural design pattern commonly used in Object-oriented programming (OOP). We also demonstrate how the sequence decorator can be applied to stressing DUT with massive concurrent transitioning state space like an out-of-order processor cluster network.

Chi-Ming Li, Synopsys Inc., Hsinchu City, Taiwan (Chi-Ming.Li@synopsys.com)

 

Speaker: Chi-Ming Li

Chi-Ming is a verification engineer at Synopsys, prior to which he worked for ARM and AnshingTek. He received a B.S. and a M.S. from NTHU EE. Chi-Ming is passionate about computing technology and has hands-on experience in several processor verification projects.