Session: UVM

Session Chair: SJ Wu, Andes

Title: UVM-based extended Low Power Library package with Low Power Multi-Core Architectures

Language: English

Abstract— This paper explores integration of Unified Power Format (UPF) and Universal Verification Methodology (UVM) to simplify the functional verification and power management process. Specifically, focuses on incorporating low power design features within multi-Core architectures using in-built low power routines in Assembly Language (ASM). The proposed Low Power UVM Package contains classes for SOC environment like Devices, Buses, and Memory, which can implement low power strategies using SystemVerilog and DPI extension within proposed Low Power UVM Package during the Run Phase of UVM Agents. The aim is to enable efficient power management and bridge the gap between functional verification and power management engineers.

Avnita Pal, VLSI Design Engineer, Silicon Interfaces, Mumbai, India (avnita@siliconinterfaces.com)
Priyanka Gharat, VLSI Design Engineer, Silicon Interfaces, Mumbai, India (priyanka@siliconinterfaces.com)

Speaker: Priyanka Gharat

Priyanka Gharat is a highly skilled VLSI Design Engineer, Researcher and PredCaster™ at Silicon Interfaces with extensive work on Low Power, multi-Core Computational Logic, Single Intent cross axes Portability, Methodologies, like UVM/PSS, and Fault Simulation. Priyanka is a co-author to UPVM™ for low power integration with UVM platform, application of AI-ML to Fault Simulation and has presented at 59th DAC USA, DVCon India and at 60th DAC  USA on Vedic multiplier and also attended DVCon Europe at Munich and was scheduled to speak at canceled DATE D&R IP-SOC, France Feb 2020. Priyanka has a Masters’s Degree in Electronics, and lives in beautiful Nhava Sheva port city near Navi Mumbai with a wonderful forward-looking family.