Session: UVM

Session Chair: SJ Wu

Title: Scoreboards and Checkers Memory, TLB and Cache

Language: English

Abstract—SystemVerilog UVM provides a clean, methodical way to generate stimulus, collect coverage and write checkers. This paper focuses on scoreboards and checkers for memory-based system, including in-order transactions and out-of-order transactions.

Rich Edelman, Siemens EDA, Fremont, CA US (rich.edelman@siemens.com)

Speaker: Chih-Hsiang Liu

Hello, I am an AE Consultant at Siemens EDA who is a DV enthusiast. Prior to Siemens EDA, I have more than 15 years of digital design verification experience in different IC design companies. I enjoy to research something new about DV, especially in development and deployment of CRV/coverage driven verification methodology.

Welcome to research with me together.