Session: UVM

Session Chair: SJ Wu, Andes

Title: Improve the quality of SystemC IPs through coverage-driven random verification

Language: English

Abstract—The development of SystemC IPs is mainly focused on a short period. Realizing that SystemC IPs can be improved to get higher quality while keeping a good period, we apply UVM to SystemC verification to add coverage-driven random verification besides directed testing. Our solution has the same structure as UVM in SystemVerilog. It provides constraint random by CRAVE and functional coverage by FC4SC. We tried it on a verified SystemC IP. Using directed testing, it originally took 18 man-months and found 127 bugs. We spent about 21 man-months on coverage-driven random verification and found 38 more bugs, 50% of which are hard cases.

Trung Pham, Renesas Electronics Corporation, Ho Chi Minh City, Vietnam (trung.pham.zn@renesas.com)

Huy Phan, Renesas Electronics Corporation, Ho Chi Minh City, Vietnam (huy.phan.wh@renesas.com)

Masayuki Masuda, Renesas Electronics Corporation, Tokyo, Japan (masayuki.masuda.gx@renesas.com)

Speaker: Trung Pham

• Assistant Manager at Renesas Design Vietnam Co., Ltd.
• 6 years of experience in SystemC modeling for virtual platform.
• 1 year of experience in UVM application for RTL-IP verification.
• Recent trial of UVM-SystemC for SystemC-IP verification and achieved the Company Annual Award last year.