Session: Mixed Signal Design and Verification

Session Chair: Ted Chou

Title: Design and Verification of a Cell-Based PLL using an Optimized DCO

Language: Mandarin

Abstract—The Digitally Controlled Oscillator (DCO) is a key component in a cell-based Phase-Locked Loop (PLL) for on-chip high-speed clock generation. In this work, we design a cell-based DCO to achieve a more linear DCO period profile with a consistently small resolution of just 1ps. This DCO is embedded into an in-house PLL to evaluate its impact on the output clock period jitter. For verification, a mixed-level simulation method is applied to speed up the process, in which the data-path of the PLL is modeled in the transistor level while the controller in the RTL. Post-layout simulation results reveal that our DCO can achieve a resolution in the range of [0.62ps, 1.25ps] for all 5 process corners in the most extreme temperature range from -40˚C to 150˚C. At the same time, peak-to-peak jitter of our PLL over 2000 clock cycles after locking is reduced from the original 10.86ps to 6.07ps, with a reduction ratio of (10.86-6.07)/10.86 = 44%. Last, but not the least, we show the results of using our PLL to perform online speed grading for arithmetic circuits.

Yi-Sheng Wang            Hsiang-Kai Teng           Shi-Yu Huang

Electrical Engineering Department, NTHU, Taiwan

Speaker: Yi-Sheng (Jason) Wang

Yi-Sheng Wang received the B.S. degrees in electrical engineering from National Central University, Taoyuan, Taiwan, in 2021. He is currently working towards the M.S. degrees in electrical engineering at National Tsing Hua University, Hsinchu, Taiwan. His research interests include all-digital phase-locked loop (ADPLL) design and its application.