Session: AI

Session Chair: YJ Chen, Realtek

Title: AI-Driven Verification

Language: Mandarin

Abstract: Chips are getting bigger and more complex these days, and managing regression is a huge task for tape-out. Our solution applies AI/ML technology on failure classification, waveform mining, semantic differentiation, and auto pin down the error code. In addition, ML enables simulations to stress test corner cases more efficiently than traditional regression and expose bug signature faster on the areas of interest. Applying machine learning, engineers can reduce simulation cycle times by a factor of 5+, achieve the same level of coverage.

Curtis Tsai, Cadence Design Systems, Hsinchu City, Taiwan (curtist@cadence.com)

Stanley Chen, Cadence Design Systems, Hsinchu City, Taiwan (stanleyc@cadence.com)

Speaker: Curtis Tsai

Curtis Tsai is a Sr Principal Customer Engagement Engineer at Cadence, where he has been working since 2015. He holds a master’s degree in electronic engineering from National Chiao Tung University, and specializes in promoting frontend tools and applications, such as Verisium Apps/Debug, XceliumML, Low Power Simulation, multicore simulation, and more. He is passionate about helping customers solve various design and verification challenges, and providing the best technical solutions and support.