Paper 2.3 – Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset

September 7, 2023 from 2:30 pm to 3:00 pm

  • Track 2
  • 階梯教室
Speaker: Gopi Srinivas Deepala - Silicon Interfaces

Session: AI

Session Chair: YJ Chen, Realtek

Title: Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset

Language: English

Abstract— This paper applies AI/ML algorithms to reduce fault simulation cycles, replacing standard techniques where each node is switched with Stuck@0/Stuck@1 by generation, testability, and simulation. AI/ML techniques partition datasets, build/compile ML models, and perform model fitting with error reduction techniques such as optimization and activation/loss functions. Predicted match results run through different sized datasets and hyper-parameters resulted in a 20% reduction in
simulation cycles. The paper also analyzes the SafeSPI protocol and its “safing” features, such as monitoring sensors, adding CRC checks for error detection and fault tolerance. The protocol is analyzed using ISO26262 Safety Verification simulation, ensuring accurate data transmission by detecting potential bugs with Stuck@0/@1 injection.

Darshan Sarode, VLSI Design Engineer, Silicon Interfaces, Mumbai, India
(darshan@siliconinterfaces.com)
Pratham Khande, VLSI Design Engineer, Silicon Interfaces, Mumbai, India
(pratham@siliconinterfaces.com)
Gopi Srinivas Deepala, VLSI Design Engineer, Silicon Interfaces, Mumbai,
India(gopi@siliconinterfaces.com)
Priyanka Gharat, VLSI Design Engineer, Silicon Interfaces, Mumbai, India
(priyanka@siliconinterfaces.com)
Avnita Pal, VLSI Design Engineer, Silicon Interfaces, Mumbai, India
(avnita@siliconinterfaces.com)

Speaker: Gopi Srinivas Deepala

Gopi Srinivas Deepala is a dynamic VLSI Design Engineer and Research at Silicon Interfaces with fundamental and indepth knowledge on methodologies such as UVM and has good skills on System Verilog. Gopi’s key research area is on Diagnostic Coverage and Fault Simulation with Artificial Intelligence and Machine Learning (AI/ML) and IP SafeSPI for the Automotive segments and Function Safety. Gopi has articles to his credit at Verification Horizon for Safing of SafeSPI. Gopi holds a Bachelor of Engineering (Electronics & Communication Engineering), India and lives in the flamingo city of Navi Mumbai independently.