Session: Formal Verification

Session Chair: Prosper Chen, AMD

Title: Formal Sign-off methodology for IP blocks

Language: Mandarin

Abstract — Coverage driven simulation-based verification is used as the primary verification methodology for modern SoC designs. It requires a lot of effort to build the test environments, from IP blocks, to sub-systems and finally the SoC system. Implementing comprehensive coverage metrics is critical, but also error-prone and time-consuming. Moreover, functional coverage metrics are often incomplete when design features change dynamically, resulting in coverage holes. We augment the UVM simulation-based sign-off process with formal verification to deliver high quality devices and we apply formal techniques where it improves effectiveness and productivity. We use several formal methods, and block level formal sign-off in the SoC verification process. This paper discusses the formal sign-off methodology for IP blocks in our SoC designs.

Anna Chang, Chia-An Hsu
Google Inc., New Taipei City, Taiwan
annacha@google.com, chiaan@google.com

Speaker: Anna Chang

Hi, My name is Anna Chang. I work in the ISP team at Google and we design the chips for Google Mobile devices. Before that I worked on networking products such as Tomahawk and Trident at Broadcom, Inc for mega data centers including Google. I use UVM and Formal methodology, and my focus is on flow automation. I graduated from UCLA with a master’s degree in Electrical Engineering. In my spare time, I enjoy music, reading, and documentary films.