Session: Assertion

Session Chair: Prosper Chen, AMD

Title: A Novel Approach to Accelerate Latency of Assertion Simulations

Language: English

Abstract—RTL assertions are used in assertion-based verification (ABV) to capture design intent and provide portable monitors that check for correct behavior. Assertions improve observability coverage and error localization during simulation, reducing debug time significantly. However, ABV simulation can be slowed down by extra simulation events. In this paper, we present a novel approach to accelerate ABV simulation. We first create a light-weight ABV environment to minimize the number of simulation events. Then, we decouple the Testbench/DUT and the assertions. This allows us to record the Testbench/DUT simulation stimulus to waveforms and replay them to the assertions. Finally, we enable parallel waveform replay with a smaller number of assertions for each run. Our experimental results show that our approach can reduce the assertion simulation overhead by 57% on average.

Jack Yen, Synopsys Inc., Hsinchu, Taiwan (jackyen@synopsys.com)
Felix Tung, Synopsys Inc., Hsinchu, Taiwan (yatung@synopsys.com)

Speaker: Dr. Jack Yen

Jack (Chia-Chih) Yen is an R&D leader in Synopsys Inc.. With 10+ years of experience in EDA, he is deeply passionate about delivering practical and optimal solutions that benefit both customers and the company. Jack’s expertise lies in several areas, including verification for Systems-on-Chip (SoCs) and post-silicon Netlist, power analysis and optimization, as well as leveraging AI and machine learning in EDA applications. Prior to Synopsys, Jack spent 7 years in Springsoft Inc.. He holds a PhD from National Chiao-Tung University in Taiwan, specializing in formal and semi-formal verification of hardware designs.