Title: Augment and Automate Formal for Designers

Abstract:

This tutorial explains the various Formal enabled checks/verification capabilities which can be used by designers. It also describes how these can be easily deployed when these are integrated in the RTL Designer’s regular check-in, regression and milestone signoff tasks.

Speaker: Kanwar Pal Singh, Product Engineering Group Director, Cadence

Kanwar Pal Singh is a Product Engineering Group Director in Cadence System Verification Group. He has 23 years of experience in EDA industry, which is primarily Cadence. At Cadence he has rich experience of working on various verification technologies and over years has witnessed the evolution of Verification solutions. He currently works in the Static and Formal Verification domain i.e Jasper product line, where his focus is on the RTL Signoff technologies. He has presented in various international conferences and holds 4 patents in this domain.