Title: Better Late Than Never – Collecting Coverage From Ones and Zeroes

Speaker: Tsungyu Tsai and Rich Edelman, Siemens

This paper lays out a flow and strategy to read a test vector file of ones and zeroes captured from simulation, emulation, tester or elsewhere, and then applies those test vectors to a SystemVerilog coverage model and generates coverage reports. This technique can help understand the coverage that is represented by the captured tests – the ones and zeros.