The Design & Verification Conference (DVCon) is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated circuits. 

This highly technical conference focuses on the practical aspects of design and verification techniques and the use of standards in leading-edge projects, with the goal of facilitating the improvement and maturation of design and verification techniques throughout the industry by encouraging attendees to adopt and reference similar techniques in their own development flow. 

The DVCon Taiwan Steering Committee invites submissions of papers and presentations on practical experiences and novel applications of standards in various areas. Submissions on topics in the following areas are encouraged, but not limited to:

■ Verification and Validation

• Advanced methodologies and test-benches
• Verification processes, regressions and resource management
• Debug and analysis of complex designs
• Multi-language design and verification
• Hardware/Software co-design and co-verification of embedded systems

■ Design and Verification Reuse / Automation

• Bridging verification and validation across multiple engines SoC and IP integration methods and tools
• Applications of the Accellera Portable Stimulus Standard
• Configuration management of IP and abstraction levels
• Interoperability of models and/or tools
• High-level synthesis from ESL languages
• Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping

■ Machine Learning and Big Data

• Automating the Optimization of Verification / Implementation Processes
• Coverage metrics and data analysis
• Performance modeling and/or analysis

■ Low-Power Design and Verification

• Low-power design and verification
• Clock domain crossing verification
• Power modeling, estimation and management

■ Safety-Critical / Security-Critical Design and Verification

• Verification and DO-254 compliance
• Automotive ISO 26262 Design and Verification Challenges
• Medical or Industrial Verification Challenges
• Requirements-Driven Verification Methodologies
• IP protection and security

■ Mixed-Signal Design and Verification

• Mixed-signal design & verification techniques
• Real-value modeling approaches
• Application of mixed-signal extensions for UVM

 In addition to the specific topic areas suggested above, submissions may incorporate:

• Usage of Electronic Design Automation (EDA) tools such as simulation, emulation, formal verification, virtual prototyping and/or FPGA prototyping
• FPGA-based designs
• Usage of specialized design and verification languages such as SystemVerilog, SystemC, and e
• Assertions in SVA or PSL
• The use of general purpose and scripting languages such as C, C++, Perl, Python, Tcl and others
• Applications of the Accellera Portable Stimulus Standard
• Applications of design patterns or other innovative language techniques
• The use of AMS languages
• Internet of Things applications