2025/09/09

08:30 – 09:00	Registration
09:00 – 09:20	Opening	Robert, Chi-Kang Chen, General Chair, DVCon Taiwan				Grand opening of 3rd DVCon Taiwan
09:20 – 10:00	Moderator	Nan-Sheng Huang, Nan-Sheng Huang, Mediatek
	Keynote Speaker 1	Chinh Tran, Deputy General Manager, MediaTek				Topic: A Global Journey in Design Verification: History, Challenges, and Outlook
10:00 – 10:40	Moderator	Ying-Cherng Lan, AE Director, Cadence
	Keynote Speaker 2	Matt Graham, Sr. Group Director, Cadence				Topic: Harnessing Agentic-AI to Accelerate Verification
10:40 – 11:00	Morning Break (Setting up the stage for Panel Discussion)
11:00 – 12:00	Moderator	Prof. Chun-Yi Lee (李濬屹教授), Department of Computer Science and Information Engineering National Taiwan University
	Panel Discussion	William Wang, Founder and CEO, ChipAgents Jim Kung, Sr. Manager, MediaTek Jack Yen, Sr. Director, Synopsys Matt Graham, Sr. Group Director, Cadence Dan Yu, Senior AI Innovation Manager, Siemens EDA Takahide Yoshikawa, Technical Program Chair, DVCon Japan, Fujitsu				Topic: The Dawn of GenAI in Design and Verification
12:00 – 13:20	Lunch Break
Session Host	Alan Su / Eric Chen			Michael Chiang / Tina Yin			Philips Tsai / Martin Chen
	Track 1-1	Speaker	Topic	Track2-1	Speaker	Topic	Track 3-1	Speaker	Topic
13:20 – 13:40	Session 1.1 ( 30 mins talk + 10 mins Q&A )	Genichi Tanaka General Chair DVCon Japan	DVCon Japan at a galance1 and Japan Semiconductor trend	Sessions 2.1	Shi Feng Chen and Ning Yuan Cheng TESDA	AutoDV – Click, Vhf, and Relax	Sessions 3.1	Jonah Chen GUC	Distributed Compile/Simulation Techniques for Tackling AI/HPC SoC DV
13:40 – 14:00				Sessions 2.2	Seungwhun Paik Baum	Taming Operational Power in Early Design Stage	Sessions 3.2	Vita Liao Synopsys	Harnessing AI/ML for Superior Regression Management – Boost Verification Efficiency
14:00 – 14:20	Session 1.2a ( 60 mins talk )	Aiyush Aggarwal Accellera CDC Working Group	CDC-RDC Inter-operable collateral Standardization	Sessions 2.3	Andy Stein Breker	Fast IP/SoC Test Generation with SystemVIPs and Test Suite Synthesis	Sessions 3.3	Andy Lee Synopsys	EP-Ready Hardware-Assisted-Verification Platforms
14:20 – 14:40				Sessions 2.4	Susmita Mistri, Hao-Chung Kuo and Chang-Ching Tu NYCU, Surya Elangovan	Dfynamic Switching Performance of GaN HEMTs in Boost Converter Topology Using Double Pulse Test (DPT) with Parasitic-Induced Effects	Sessions 3.4	Chih Jen Wei Phison	Automatically Fix RTL Lint Violations with GenAI
14:40 – 15:00				Sessions 2.5	CY Chang Siemens EDA	Formal-driven assurance of RISC-V Cores with AI-Ready FPUs	Sessions 3.5	Sridhar Mukund Silicon Interfaces	Secur e Multi-CPU Memory Access in PCIe via Tokenized Address Space Management
15:00 – 15:20	Afternoon Break
Session Host	Alan Su, NCKU / Eric Chen			Ted Chou, Cadence / Tina Yin			Yung Jen Chen, Realtek / Martin Chen
	Track 1-2	Speaker	Topic	Track2-2	Speaker	Topic	Track 3-2	Speaker	Topic
15:20 – 15:40	Session 1.2b ( 30 mins talk + 10 mins Q&A )	Aiyush Aggarwal Accellera CDC Working Group	DC-RDC Inter-operable collateral Standardization	Sessions 2.6	Rich Edelman Siemens EDA	Debugging RTL with Transactions – Small, simple changes enabling higher level understanding	Sessions 3.6	Chandini Prudvi Silicon Interfaces	UPF Centric Agentic Tool for UPVM frameworks Seamessly Integrated to Low Power ASICs
15:40 – 16:00				Sessions 2.7	Satish Kumar Padhi – VIP Cadence	Efficient Debug Strategies for PCIe Gen6 Verification Using Verification IP (VIP)	Sessions 3.7	Tanay Biradar ChipAgents	Taming the Waveform Tsunami: Agentic AI for Smarter Debugging
16:00 – 16:20	Session 1.3	Prosper Chen Google	Portable Stimulus Tutorial: Multi‑Core Interoperability	Sessions 2.8	Yuan-Teng Chang and Wenbo Zheng Siemens EDA	A Video Entropy Coder Design and Verification Using HLS and HLV	Sessions 3.8	William Wang ChipAgents	How Agentic AI is Reinventing Chip Design and Verification
16:20 – 16:40	Session 1.4	Rahil Jha, Shyam Shar and Krunal Kapadiya Cadence	Nailing Down the Debug Complexities of Complex Device Inter-Connect’s Signal Pattern	Sessions 2.9	Robert Lu Cadence	Elevate Your SOC Strategy with Helium Studio	Sessions 3.9	Yichiang Chang, Lisa Wang and Qian Wang Arteris IP	Modernizing the Hardware / Software Interface – Life beyond spreadsheets, how to bring your SoC register design into the 21st Century
16:40 – 17:00		Preparing for closing and lucky draw.		Sessions 2.A	Vatsal Patel, Ritesh Desai, Dharini Subashchandran and Ujash Poshiya Cadence	Accelerate Verification, Streamline Challenges: A Comprehensive HBM Model Solution	Sessions 3.A	Tsung-Yu Tsai Siemens EDA	Sanity Test Case Selection by Machine Learning Approach
17:00 – 17:30	Closing, Awards, and Lucky Draw.
17:40 – 20:40	VIP Banquet (Invited), Leith Castle, 2F.

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