Keynote 1: May the Dependability Be with You: Reliability and Resilience Challenges in SoC Design
Please send your request to <anardi@synopsys.com>
Keynote 2: Formal Verification: Past, Present, and Future
Please send your request to <tw_event@cadence.com>
Keynote 3: Empowering Innovation in Logic Verification: Harnessing Collective Wisdom Across Tools, Processes, and People
Session 1.1: AI & Automotive – NoC IP & Verification “A Futuristic Vision”
Please send your request to <saurabh.agarwal@truechip.net>
Session 1.2: Improving UVM test benches using UVM Run time phases
Session 1.3: Solving Memory Configurations Challenge with SVRAND Verification Flow
Session 1.4: The RTL-Level SDC Timing Exception Verification
Please send your request to <ChienLin.Huang@mediatek.com>
Session 1.5: Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices
Session 1.6: Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS)
Session 1.7: Left-shifting Testbench Development Using Environment Inversion in UVM
Session 1.8: Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores
Session 2.1: The ASIC Renaissance – A glance into the future SoC enablement
Session 2.2: Trojan Horse Detection for RISC-V Cores Using Cross-Auditing
Session 2.3: Integrated verification ecosystem for regression management, coverage convergence, and debug automation
Session 2.4: Conquering UCIe 1.1 Multi-die System Verification Challenges
Please send your request to <vagrawal@synopsys.com>
Session 2.5: Enable power-aware UPF emulation on Palladium
Please send your request to <tw_event@cadence.com>
Session 2.6: Augment and Automate Formal for Designers
Please send your request to <tw_event@cadence.com>
Session 2.7: Better Late Than Never – Collecting Coverage From Ones and Zeroes
Session 2.8: A Comprehensive Data-Driven Function Verification Process
Session 3.1: AutoDV: Boost SoC Verification by Automatic Construction
Session 3.2: SOC Verification for RISC V– “Ensuring Faster Time to Market”
Please send your request to <saurabh.agarwal@truechip.net>
Session 3.3: Low-Power Design Methodology for Early Design Stage
Please send your request to <seungwhun.paik@baum-ds.com>
Session 3.4: Automating the Integration Workflow with IP-Centric Design
Please send your request to <vlin@perforce.com>
Session 3.5: Boost SoC Development Efficiency with Arteris SoC Integration Automation Software – Automate Design Flow and Register Management